Descriptions:
Bloomberg Technology interviews the founder of a stealth AI chip startup — a former Google TPU engineer named Ryan — about raising a $500 million Series B to build a next-generation inference accelerator designed to challenge Nvidia’s dominance in AI compute. The round was led by quantitative trading firm Jane Street and Situational Awareness, the fund run by Leopold Aschenbrenner, known for his influential writing on AGI development timelines. The size and investor profile of the raise signals unusually high conviction in both the technical approach and the market opportunity.
The core architectural thesis is a hybrid chip that combines High Bandwidth Memory (HBM) and SRAM in a single product — something no existing chip does at scale. Current chips specialize in one or the other: Nvidia, Google, and Amazon use HBM-based designs for throughput, while Cerebras and Groq use SRAM for latency. The startup claims its design matches or exceeds the best of both worlds, achieving superior FLOPS per square millimeter while maintaining low inference latency. To get there, the team made a deliberate choice to abandon backward compatibility with prior chip generations, allowing a blank-slate architecture optimized exclusively for large language model workloads — featuring very large matrix operations and low-precision compute support.
On the production roadmap, the company plans to complete final chip design in 2026 and begin manufacturing and shipping in 2027. TSMC is identified as the logic wafer supplier, with SK Hynix, Samsung, and Micron as candidate HBM memory partners. The founder also addresses why this venture might succeed where Groq — recently acquired by Nvidia — struggled to find independent scale.
📺 Source: Bloomberg Technology · Published February 24, 2026
🏷️ Format: Interview
